SSD1306Z datasheet(48/65 Pages) ETC2

48 / 65 page

Solomon Systech

Apr 2008 P 48/59

Rev 1.1

SSD1306

12 DC CHARACTERISTICS

Condition (Unless otherwise specified):

Voltage referenced to VSS

VDD = 1.65 to 3.3V

TA = 25

°C

Table 12-1 : DC Characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

VCC

Operating Voltage

VDD

Logic Supply Voltage

1.65

3.3

VOH

High Logic Output Level

IOUT = 100uA, 3.3MHz

0.9 x VDD -

VOL

Low Logic Output Level

IOUT = 100uA, 3.3MHz

0.1 x VDD V

VIH

High Logic Input Level

0.8 x VDD -

VIL

Low Logic Input Level

0.2 x VDD V

ICC, SLEEP ICC, Sleep mode Current

VDD = 1.65V~3.3V, VCC = 7V~15V

Display OFF, No panel attached

IDD, SLEEP IDD, Sleep mode Current

VDD = 1.65V~3.3V, VCC = 7V~15V

Display OFF, No panel attached

ICC

VCC Supply Current

VDD = 2.8V, VCC = 12V,

IREF = 12.5uA

No loading, Display ON, All

430

780

IDD

VDD Supply Current

VDD = 2.8V, VCC = 12V,

IREF = 12.5uA

No loading, Display ON, All

Contrast = FFh

150

Contrast=FFh

100

Contrast=AFh

ISEG

Segment Output Current

VDD=2.8V, VCC=12V,

IREF=12.5uA, Display ON.

Contrast=3Fh

Dev

Segment output current

uniformity

Dev = (ISEG – IMID)/IMID

IMID = (IMAX + IMIN)/2

ISEG[0:131] = Segment current at

contrast = FFh

-3

Adj. Dev

Adjacent pin output current

uniformity (contrast = FF)

Adj Dev = (I[n]-I[n+1]) /

(I[n]+I[n+1])

-2

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