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VSC8504-02 Datasheet(PDF) 24 Page - Microsemi Corporation |
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VSC8504-02 Datasheet(HTML) 24 Page - Microsemi Corporation |
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24 / 131 page  Functional Descriptions VMDS-10507 VSC8504-02 Datasheet Revision 4.2 13 addition, set register 18G as desired. The device also supports SGMII MAC-side autonegotiation on each individual port and is enabled through register 16E3, bit 7, of that port. Figure 16 • QSGMII MAC Interface 3.3 SerDes Media Interface The device SerDes media interface performs data serialization and deserialization functions using an integrated SerDes block in the SerDes media interface. The interface operates at 1.25 Gbps speed, providing full-duplex and half-duplex for 10/100/1000 Mbps bandwidth that can connect directly to 100BASE-FX/1000BASE-X-compliant optical devices as well as to 10/100/1000BASE-T copper SFP devices. The interface also provides support for unidirectional transport as defined in IEEE 802.3-2008, Clause 66. The SerDes interface has the following operating modes: • QSGMII/SGMII to 1000BASE-X • QSGMII/SGMII to 100BASE-FX • QSGMII/SGMII to SGMII/1000BASE-X protocol transfer The SerDes media block has the termination resistor integrated into the device. It also has the AC decoupling capacitors integrated in the receive path. A software reset through register 0, bit 15 is required when changing operating modes between 100BASE-FX and 1000BASE-X. 3.3.1 QSGMII/SGMII to 1000BASE-X The 1000BASE-X SerDes media in QSGMII/SGMII mode supports IEEE 802.3 Clause 36 and Clause 37, which describe 1000BASE-X fiber autonegotiation. In this mode, control and status of the SerDes media is displayed in the VSC8504-02 device registers 0 through 15 in a manner similar to what is described in IEEE 802.3 Clause 28. In this mode, connected copper SFPs can only operate at 1000BASE-T speed. A link in this mode is established using autonegotiation (enabled or disabled) between the PHY and the link partner. To configure the PHY in this mode, set register 23, bits 10:8 = 010. To configure 1000BASE-X autonegotiation for this mode, set register 0, bit 12. Setting this mode and configurations can be performed individually on each of the four ports. Ethernet packet generator (EPG), cyclical redundancy check (CRC) counters, and loopback modes are supported in 1000BASE-X mode. 3.3.2 QSGMII/SGMII to 100BASE-FX The VSC8504-02 supports 100BASE-FX communication speed for connecting to fiber modules such as GBICs and SFPs. This capability is facilitated by using the connections on the SerDes pins when connected to a MAC through QSGMII/SGMII. Ethernet packet generator (EPG), cyclical redundancy check (CRC) counters, and loopback modes are supported in the 100BASE-FX mode. Setting this mode and configurations can be performed individually on each of the four ports. To configure the PHY in this mode, set register 23, bits 10:8 = 011. QSGMII MAC TxP TxN RxN RxP TxP TxN RxN RxP 0.1 µF 0.1 µF 0.1 µF 0.1 µF 100 Ω 100 Ω 100 Ω PHY Port_0 PHY Port_1 PHY Port_2 PHY Port_3 |
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