VSC8504-02 datasheet(25/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

3.3.3

QSGMII to SGMII Protocol Conversion

QSGMII to SGMII (protocol transfer) mode is a feature that links a fiber module or triple speed

10/100/1000-T copper SFP to the QSGMII MAC through the device. SGMII can be converted to QSGMII

with protocol conversion using this mode.

To configure the PHY in this mode, set register 23, bits 10:8 = 001. To establish the link, assert the

relevant signal-detect pin.

All relevant LED modes are supported except for collision, duplex, and autonegotiation fault. The triple-

speed copper SFP’s link status and data type plugged into the port can be indicated by the PHY’s LEDs.

Setting this particular mode and configuration can be performed individually on each of the four ports

within a QSGMII grouping.

3.3.4

Unidirectional Transport for Fiber Media

The VSC8504-02 device supports IEEE 802.3ah for unidirectional transport across its 1000BASE-X and

100BASE-FX fiber media. This feature enables transmission across fiber media, regardless of whether

the PHY has determined that a valid link has been established (register 1, bit 2). The only valid operating

modes for unidirectional fiber mode are 100BASE-FX or 1000BASE-X fiber media.

To enable this feature, set register 0, bit 5 to 1. For status of the unidirectional ability, read register 1,

bit 7.

Note: Automatic media sensing does not work with this feature. In addition, because unidirectional fiber media

must have autonegotiation disabled, SGMII autonegotiation must also be disabled (register 16E3,

bit 7 = 0).

3.4

PHY Addressing and Port Mapping

This section contains information about PHY addressing and port mapping.

3.4.1

PHY Addressing

The VSC8504-02 includes three external PHY address pins, PHYADD[4:2], to allow control of multiple

PHY devices on a system board sharing a common management bus. These pins set the most

significant bits of the PHY address port map. The lower two bits of the address for each port are derived

from the physical address of the port (0 to 3) and the setting of the PHY address reversal bit in register

20E1, bit 9.

3.4.2

SerDes Port Mapping

The VSC8504-02 includes seven 1.25 GHz SerDes macros and one 5 GHz enhanced SerDes macro.

Three of the seven SerDes macros are configured as SGMII MAC interfaces and the remaining four are

configured as 1000BASE-X/100BASE-FX SerDes media interfaces. The enhanced SerDes macro can

be configured as either a QSGMII MAC interface or the fourth SGMII MAC interface. The following table

shows the different operating modes based on the settings of register 19G, bits 15:14.

3.5

Cat5 Twisted Pair Media Interface

The VSC8504-02 twisted pair interface is compliant with IEEE 802.3-2008 and the IEEE 802.3az-2010

standard for energy efficient Ethernet.

Table 2 •

MAC Interface Mode Mapping

19G[15:14]

Operating Mode

SGMII

QSGMII

Reserved

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