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845GL Datasheet(PDF) 103 Page - Intel Corporation |
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845GL Datasheet(HTML) 103 Page - Intel Corporation |
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103 / 193 page ![]() Intel® 82845G/82845GL/82845GV GMCH Datasheet 103 Register Description 3.5.4.2 DRTC—DRAM Read Throttling Control Register (Device 6) Address Offset D8h Default Value 0000000000000000h Access R/W, L Size: 64 bits Bits Description 63:41 Intel Reserved. 40:28 Global Read Hexword Threshold (GRHT). The thirteen-bit value held in this field is multiplied by 2 15 to arrive at the number of hexwords that must be read within the Global DRAM Read Sampling Window in order to cause the throttling mechanism to be invoked. 27:22 Read Throttle Time (RTT). This value provides a multiplier between 0 and 63 which specifies how long Counter based read throttling remains in effect as a number of Global DRAM Read Sampling Windows. For example, if GDRSW is programmed to 1000_0000b and RTT is set to 01_0000b, then read throttling will be performed for 8192*105 host clocks (at 100 MHz) seconds once invoked (128 * 4*105 host clocks * 16). 21:15 Read Throttle Monitoring Window (RTMW). The value in this register is padded with 4 zeros to specify a window of 0–2047 host clocks with 16 clock granularity. While the throttling mechanism is invoked, DRAM reads are monitored during this window. If the number of hexwords read during the window reaches the Read Throttle Hexword Maximum, read requests are blocked for the remainder of the window. 14:3 Read Throttle Hexword Maximum (RTHM). The Read Throttle Hexword Maximum defines the maximum number of hexwords between 0–4095 which are permitted to be read from DRAM within one Read Throttle Monitoring Window. 2:1 Read Throttle Mode (RTMode). 00 = Throttling via Counters and Hardware throttle_on signal mechanisms Disabled. 01 = Reserved 10 = Counter mechanism controlled through GDRSW and GRHT is enabled. When the threshold set in GDRSW and GRHT is reached, throttling start/stop cycles occur based on the settings in RTT, RTMW, and RTHM. 11 = Reserved 0 START Read Throttle (SRT). Software writes to this bit to start and stop read throttling. 0 = Read throttling stops and the counters associated with RTMW and RTHM are reset. 1 = Read throttling begins based on the settings in RTMW and RTHM, and remains in effect until this bit is reset to 0. |
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