845GL datasheet(173/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

173

Testability

In the GMCH, testability for Automated Test Equipment (ATE) board level testing has been

implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin

connected to it.

8.1

XOR Test Mode Initialization

XOR test mode can be entered by driving GSBA[6] and GSBA[7] low, and TESTIN# low, and

PWROK low, and RSTIN# low, then drive PWROK high, then RSTIN# high. XOR test mode via

TESTIN# does not require a clock.

8.2

XOR Chain Definition

The GMCH has nine XOR chains. The XOR chain outputs are driven out on the DDR output pins

(see Table 8-1).

Table 8-2, Table 8-3, and Table 8-4 show the XOR chain pin mappings and their monitors for the

GMCH.

Note: Only AGP differential STROBEs are on different chains but in the same channel group. The rest of

the interfaces’ STROBEs are on the same chain, since they do not require opposite polarity at all

the times. All XOR chains can be run in parallel except chains with AGP strobes. Thus, chain 0 and

chain 1 cannot be run in parallel; similarly chain 2 and chain 3.

Note: The Channel A and Channel B output pins for each Chain show the same output.

Table 8-1. XOR Chain Output Pins

XOR Chain

DDR Output Pin

Channel A

DDR Output Pin

Channel B

SMAA_0

SMAA_7

SMAA_1

SMAA_8

SMAA_2

SMAA_9

SMAA_3

SMAA_10

4SMAA_4

SMAA_11

SMAA_5

SMAA_12

6SMAA_6

SWE#

SRAS#

SCAS#

SBA_0

SBA_1

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