845GL datasheet(184/193 Pages) INTEL

184 / 193 page

Intel® 82845GL/82845GV GMCH

184

Intel® 82845G/82845GL/82845GV GMCH Datasheet

ATTBASE

— Aperture Translation Table Register (Device 0)

Address Offset

B8–BBh

Size:

32 bits

AMTT

— AGP MTT Control Register (Device 0)

Address Offset

BC–BFh

Size:

8 bits

LPTT

— AGP Low Priority Transaction Timer Register (Device 0)

Address Offset

BDh

Size:

8 bits

9.4.1.2

Device 0 Register Bit Differences

The registers described in this section are in both the 82845G and 82845GL/82845GV. However,

some of the register bits have different functions/operations between the components. Only the bits

that are different are shown in this section. Thus, the bit descriptions shown in this section only

apply to the 82845GL or 82845GV. The remaining register bits are the same for all three

components and are described in Chapter 3.

GC—Graphics Control Register (Device 0)

Address Offset

52h

Default Value

0000_0000b

Access

Size:

8 bits

Bits

Description

Integrated Graphics Disable (IGDIS).

The GMCH’s Device 1 is disabled such that all

configuration cycles to Device 1 flow through to the hub interface. Also, the Next_Pointer field in

the CAPREG register (Device 0, Offset E4h) is RO at 00h. This enables internal graphics

capability.

0 = Enable. Internal Graphics is enabled (default)

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