845GL datasheet(185/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

185

Intel® 82845GL/82845GV GMCH

GMCHCFG—GMCH Configuration Register (Device 0)

Address Offset

C6–C7h

Default Value

0C01h

Access

R/W, RO

Size:

16 bits

ERRSTS—Error Status Register (Device 0)

Address Offset

C8–C9h

Default Value

0000h

Access

R/WC

Size:

16 bits

ERRCMD—Error Command Register (Device 0)

Address Offset

CA–CBh

Default Value

0000h

Access

RO, R/W

Size:

16 bits

Bits

Description

(82845GL

Only)

Core/PSB Frequency Select (PSBFREQ)—RO.

The default value of this bit is set by the strap

assigned to pin PSBSEL and is latched at the rising edge of PWROK.

0 = PSB frequency is 400 MHz (PSBSEL sampled high on PWROK assertion)

1 = Indicates a processor running 533 MHz on the board. For the 82845GL, the board will not

boot.

AGP Mode (AGP/DVO#)—RO.

This bit reflects the ADD_DETECT strap value. This strap bit

determines the function of the AGP I/O signal.

0 = 2xDVO

1 = no DVO mode, internal graphics only.

When the strap is sampled low, this bit will be a 0 and DVO mode will be selected. When the

strap is sampled high, this bit will be a 1 and DVO mode will not be selected, and the internal

graphics device would be running.

Note that when this bit is set to 0 (DVO mode), Device 1 is disabled (configuration cycles fall-

through to the hub interface) and the Next Pointer field in CAPREG will be hardwired to zeros.

Bits

Description

4:0

Intel Reserved

Bits

Description

4:0

Intel Reserved

845GL Datasheet(PDF) 185 Page - Intel Corporation

845GL Datasheet(HTML) 185 Page - Intel Corporation

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