TNETV2501INPGF datasheet(23/197 Pages) TI1

23 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Control Pins

I/O/Z

The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO20 or external memory interface control signal

EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the state of

the GPIO6 pin during reset. The C0 pin is set to PGPIO20 if GPIO6 is low during reset. The

C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high during reset. The function

of the C0 pin will be set once the device is taken out of reset (RESET pin transitions from a

low to high state).

PGPIO20

I/O/Z

C, D, E,

F, G, H,

Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during reset.

The PGPIO20 signal is configured as an input after reset.

EMIF.ARE/SADS/

SDCAS/SRE

O/Z

F, G, H,

EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high during

reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state during

reset and is set to output after reset with an output value of 1.

The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used by

the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory

address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and

synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary Control

I/O/Z

C, D, E,

The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO21 or external memory interface control signal

EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of the

GPIO6 pin during reset. The C1 pin is set to PGPIO21 if GPIO6 is low during reset. The C1

pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset. The function of the C1

pin will be set once the device is taken out of reset (RESET pin transitions from a low to

high state).

PGPIO21

I/O/Z

C, D, E,

F, G, H,

Parallel general-purpose I/O. PGPIO21 is selected when GPIO6 is low during reset.

The PGPIO21 signal is configured as an input after reset.

EMIF.AOE/SOE/

SDRAS

O/Z

EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during reset.

The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by the

EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory

output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS).

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

TNETV2501INPGF Datasheet(PDF) 23 Page - Texas Instruments

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