TNETV2501INPGF datasheet(24/197 Pages) TI1

24 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Control Pins (Continued)

I/O/Z

C, D, E,

The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO22 or external memory interface control signal

EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the

GPIO6 pin during reset. The C2 pin is set to PGPIO22 if GPIO6 is low during reset. The C2

pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The function of the C2

pin will be set once the device is taken out of reset (RESET pin transitions from a low to

high state).

PGPIO22

I/O/Z

C, D, E,

F, G, H,

Parallel general-purpose I/O. PGPIO22 is selected when GPIO6 is low during reset.

The PGPIO22 signal is configured as an input after reset.

EMIF.AWE/

SWE/SDWE

O/Z

EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during reset.

The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

The EMIF.AWE/SWE/SDWE signal serves three different functions when used by the

EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory

write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE).

I/O/Z

The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO23 or external memory interface control signal

EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin during

reset. The C3 pin is set to PGPIO23 if GPIO6 is low during reset. The C3 pin is set to

EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO23

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO23 is selected when GPIO6 is low during reset.

The PGPIO23 signal is configured as an input after reset.

EMIF.ARDY

EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset.

The EMIF.ARDY signal indicates that an external device is ready for a bus transaction to

be completed. If the device is not ready (EMIF.ARDY is low), the processor extends the

memory access by one cycle and checks EMIF.ARDY again. An internal pullup is

included to disable this feature if not used. The internal pullup can be disabled through the

External Bus Control Register (XBCR).

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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