TNETV2501INPGF datasheet(29/197 Pages) TI1

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Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

EMIF − Clock Pins

ECLKIN

C, L

External EMIF input clock. ECLKIN is selected as the input clock to the EMIF when

EMIFCLKS is high.

ECLKOUT1

O/Z

E, F, M

EMIF output clock. ECLKOUT1 outputs the EMIF input clock by default but can be held

low or set to a high-impedance state through the EMIF Global Control Register 1

(EGCR1).

The ECLKOUT1 pin is always in a high-impedance state during reset. The behavior of

ECLKOUT1 immediately after reset depends on the state of GPIO6 during reset and

EMIFCLKS:

GPIO6

EMIFCLKS

ECLKOUT1 Behavior

Pin is in a high-impedance state.

Pin toggles at ECLKIN frequency.

Pin toggles at SYSCLK3 frequency.

Pin toggles at ECLKIN frequency.

ECLKOUT2

O/Z

E, F

EMIF output clock. ECLKOUT2 can be enabled to output the EMIF input clock divided by

a factor 1, 2, or 4 through the EMIF Global Control Register 2 (EGCR2). ECLKOUT2 can

also be held low or set to a high-impedance state through the EGCR2 register.

The ECLKOUT2 pin toggles with a clock frequency equal to the EMIF input clock divided

by 4 during reset. The behavior of ECLKOUT2 immediately after reset depends on the

state of GPIO6 during reset and EMIFCLKS:

GPIO6

EMIFCLKS

ECLKOUT2 Behavior

Pin is held low.

Pin toggles at one-fourth of the ECLKIN frequency.

Pin toggles at one-fourth of the SYSCLK3 frequency.

Pin toggles at one-fourth of the ECLKIN frequency.

EMIFCLKS

C, L

EMIF input clock source select. The clock source for the EMIF is determined by the

state of the EMIFCLKS pin. The EMIF uses an internal clock (SYSCLK3) if EMIFCLKS is

low. ECLKIN is used as the clock source if EMIFCLKS is high.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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