TNETV2501INPGF datasheet(71/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

Table 3−16. PLL Divider 2 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

D2EN

R/W

Divider D2 enable

D2EN = 0:

Divider 2 disabled

D2EN = 1:

Divider 2 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

PLLDIV2

4:0

R/W

00011

Divider D2 ratio (SYSCLK2 divider)

PLLDIV2 = 00000:

Divide by 1

PLLDIV2 = 00001:

Divide by 2

PLLDIV2 = 00010:

Reserved

PLLDIV2 = 00011:

Divide by 4

PLLDIV2 = 00100−11111: Reserved

3.9.5.6

PLL Divider3 Register (PLLDIV3) for SYSCLK3

This register controls the value of the divider D3 for SYSCLK3. It is in both the BYPASS and PLL paths.

D3EN

Reserved

R/W, 1

R, 0000000

Reserved

PLLDIV3

R, 000

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−20. PLL Divider 3 Register Layout (0x1C90)

Table 3−17. PLL Divider 3 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

D3EN

R/W

Divider D3 enable

D3EN = 0:

Divider 3 disabled

D3EN = 1:

Divider 3 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

PLLDIV3

4:0

R/W

00011

Divider D3 ratio (SYSCLK3 divider)

PLLDIV3 = 00000:

Divide by 1

PLLDIV3 = 00001:

Divide by 2

PLLDIV3 = 00010:

Reserved

PLLDIV3 = 00011:

Divide by 4

PLLDIV3 = 00100−11111: Reserved

TNETV2501INPGF Datasheet(PDF) 71 Page - Texas Instruments

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