ADC3541 datasheet(40/68 Pages) TI1

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7.4 Device Functional Modes

7.4.1 Normal operation

In normal operating mode, the entire ADC full scale range gets converted to a digital output with 14-bit

resolution. The output is available in as little as 1 clock cycle on the digital CMOS outputs.

7.4.2 Power Down Options

A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is

an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to

be pulled high externally to enter global power down mode.

The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in

order to trade off power consumption vs wake up time as shown in Table 7-12.

AIN

CLK

VREF

ADC

1.2V REF

REFBUF

Temp Sensor

NCO

Digital Downconverter

Dig I/F

Figure 7-38. Power Down Configurations

Table 7-12. Overview of Power Down Options

Function/ Register

PDN

via SPI

Mask for

Global PDN

Feature -

Default

Power

Impact

Wake-up

time

Comment

ADC

Yes

Enabled

ADC is included in Global PDN

automatically

Reference gain amplifier

Yes

Enabled

~ 0.4 mA

~3 us

Should only be powered down in power

down state.

Internal 1.2V reference

Yes

External ref

~ 1-3.5 mA

~3 ms

Internal/external reference selection is

available through SPI and REFBUF pin.

Clock buffer

Yes

Differential

clock

~ 1 mA

n/a

Single ended clock input saves ~ 1 mA

compared to differential.

Some programmability is available

through the REFBUF pin.

Temperature sensor

Yes

Disabled

TBD

n/a

Output interface drivers

Yes

Enabled

TBD

n/a

Depending on output interface mode,

unused output drivers can be powered

down for maximum power savings

REFSYS

Yes

Enabled

TBD

Internal bias currents

Decimation filter

Yes

Disabled

see electrical

table

n/a

ADC3541

SBAS840 – JULY 2020

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