ADC3541 datasheet(52/68 Pages) TI1

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Figure 7-54. Register 0x19

FCLK SRC

FCLK DIV

FCLK EN

TOG FCLK

R/W-0

Table 7-30. Register 0x19 Field Descriptions

Bit

Field

Type

Reset

Description

FCLK SRC

R/W

User has to select if FCLK signal comes from ADC or from DDC

block. Here real decimation is treated same as bypass mode

0: FCLK generated from ADC. FCLK SRC set to 0 for DDC

bypass, real decimation mode and 1/2-w complex decimation

mode.

1: FCLK generated from DDC block. In complex decimation

mode only this bit needs to be set for 2-w and 1-w output

interface mode but NOT for 1/2-w mode.

6-5

R/W

Must write 0

FCLK DIV

R/W

This bit needs to be set to 1 for 2-w output mode in bypass

mode only (non decimation).

0: All output interface modes except 2-w bypass mode..

1: 2-w output interface mode.

3-2

R/W

Must write 0

FCLK EN

R/W

This bit enables FCLK output for CMOS output.

0: Data output pin is used for parallel output data.

1: Data output pin is used for FCLK output in serialized CMOS

mode.

R/W

Must write 0

Table 7-31. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface

BYPASS/DECIMATION

SERIAL INTERFACE

FCLK SRC

FCLK DIV

Decimation Bypass/ Real Decimation

2-wire

1-wire

Complex Decimation

2-wire

1-wire

ADC3541

SBAS840 – JULY 2020

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