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ADC3541 Datasheet(PDF) 53 Page - Texas Instruments

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Part # ADC3541
Description  ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC
PDF  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3541 Datasheet(HTML) 53 Page - Texas Instruments

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Figure 7-55. Register 0x1B
7
6
5
4
3
2
1
0
MAPPER EN
20B EN
BIT MAPPER RES
0
1
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-32. Register 0x1B Field Descriptions
Bit
Field
Type
Reset
Description
7
MAPPER EN
R/W
0
This bit enables changing the resolution of the output (including
output serialization factor) in bypass mode only.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
6
20B EN
R/W
0
This bit enables 20-bit output resolution which can be useful for
very high decimation settings so that quantization noise doesn't
impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3
BIT MAPPER RES
R/W
000
Sets the output resolution using the bit mapper. MAPPER EN bit
(D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2
0
R/W
0
Must write 0
1
1
R/W
1
Must write 1
0
0
R/W
0
Must write 0
Table 7-33. Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/
DECIMATION
OUTPUT RESOLUTION
MAPPER EN (D7)
BIT MAPPER RES (D5-D3)
Decimation Bypass
Resolution Change
1
000: 18-bit
001: 16-bit
010: 14-bit
Real Decimation
Resolution Change (default 18-bit)
0
Complex Decimation
0
Figure 7-56. Register 0x1E
7
6
5
4
3
2
1
0
0
0
CMOS DCLK DEL
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-34. Register 0x1E Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5-4
CMOS DCLK DEL
R/W
00
These bits adjust the output timing of CMOS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
3-0
0
R/W
0
Must write 0
www.ti.com
ADC3541
SBAS840 – JULY 2020
Copyright © 2020 Texas Instruments Incorporated
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