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ADC3541 Datasheet(PDF) 55 Page - Texas Instruments |
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ADC3541 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 68 page ![]() Table 7-37. FCLK Pattern for different resolution based on interface DECIMATION OUTPUT RESOLUTION 2-WIRE 1-WIRE REAL DECIMATION 14-bit Use Default 0xFE000 16-bit 0xFF000 18-bit 0xFF800 COMPLEX DECIMATION 14-bit 0xFFFFF 16-bit 0xFFFFF 18-bit 0xFFFFF Figure 7-59. Register 0x24 7 6 5 4 3 2 1 0 0 0 0 0 0 DIG BYP DDC EN 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-38. Register 0x24 Field Descriptions Bit Field Type Reset Description 7-3 0 R/W 0 Must write 0 2 DIG BYP R/W 0 This bit needs to be set to enable digital features block which includes decimation and scrambling. 0: Digital feature block bypassed - lowest latency 1: Data path includes digital features 1 DDC EN R/W 0 Enables internal decimation filter 0: DDC disabled. 1: DDC enabled. 0 0 R/W 0 Must write 0 N DECIMATION DDC DIG BYP To output interface Scrambling SCR EN Figure 7-60. Register control for digital features www.ti.com ADC3541 SBAS840 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: ADC3541 |
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