TPS7A2033PDBVR datasheet(10/28 Pages) TI1

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DS(ON)

RATED

TPS7A20

SBVS338A – MARCH 2020 – REVISED MARCH 2020

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7.3 Feature Description

7.3.1 Low Output Noise

Any internal noise at the TPS7A20 reference voltage is reduced by a first-order, low-pass RC filter before being

passed to the output buffer stage. The low-pass RC filter has a –3-dB cut-off frequency of approximately 0.1 Hz.

7.3.2 Smart Enable

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven

above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal

pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is

connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical

Characteristics table.

This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the

output voltage.

7.3.3 Dropout Voltage

Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output

current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.

The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output

voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the

nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.

(1)

7.3.4 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the

output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the

voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output

voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-

circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output

is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the

device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If

the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

TPS7A2033PDBVR Datasheet(PDF) 10 Page - Texas Instruments

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