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TPS7A20

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SBVS338A – MARCH 2020 – REVISED MARCH 2020

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and

are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and

C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of

Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,

and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value

capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located

several inches from the input power source.

Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor

within the range specified in the Recommended Operating Conditions table for stability.

8.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in

Figure 4 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.

Figure 4. Load Transient Waveform

During transitions from a light load to a heavy load, the:

•

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

•

Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load, the:

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)