Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

CS47L24 Datasheet(PDF) 87 Page - Cirrus Logic

Part # CS47L24
Description  Low Power Audio Hub for Wearable Technology
PDF  256 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L24 Datasheet(HTML) 87 Page - Cirrus Logic

Back Button CS47L24 Datasheet HTML 83Page - Cirrus Logic CS47L24 Datasheet HTML 84Page - Cirrus Logic CS47L24 Datasheet HTML 85Page - Cirrus Logic CS47L24 Datasheet HTML 86Page - Cirrus Logic CS47L24 Datasheet HTML 87Page - Cirrus Logic CS47L24 Datasheet HTML 88Page - Cirrus Logic CS47L24 Datasheet HTML 89Page - Cirrus Logic CS47L24 Datasheet HTML 90Page - Cirrus Logic CS47L24 Datasheet HTML 91Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 87 / 256 page
background image
CS47L24
Rev 4.1
87
The bracketed numbers in Figure 28,
e.g.,”(90h)” indicate the corresponding *_SRCn register setting for selection of that
signal as an input to another digital core function.
The register bits associated with the ASRCs are described in Table 22.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3808
(0EE0h)
ASRC_EN
ABLE
3
ASRC2L_ENA
0
ASRC2 Left Enable
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
2
ASRC2R_ENA
0
ASRC2 Right Enable
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
1
ASRC1L_ENA
0
ASRC1 Left Enable
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
0
ASRC1R_ENA
0
ASRC1 Right Enable
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
R3809
(0EE1h)
ASRC_ST
ATUS
3
ASRC2L_ENA_S
TS
0
ASRC2 Left Enable Status
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
2
ASRC2R_ENA_S
TS
0
ASRC2 Right Enable Status
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
1
ASRC1L_ENA_S
TS
0
ASRC1 Left Enable Status
(Left ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
0
ASRC1R_ENA_S
TS
0
ASRC1 Right Enable Status
(Right ASRC channel from ASYNCCLK
domain to SYSCLK domain)
0 = Disabled
1 = Enabled
R3810
(0EE2h)
ASRC_RA
TE1
14:11
ASRC_RATE1
[3:0]
0000
ASRC Sample Rate select for SYSCLK
domain
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are Reserved.
The selected sample rate is valid in the
range 8kHz to 48kHz.
The ASRC_IN1L_SRC and
ASRC_IN1R_SRC registers should be set
to 00h before ASRC_RATE1.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com