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CS47L24 Datasheet(PDF) 21 Page - Cirrus Logic |
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CS47L24 Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 256 page  CS47L24 Rev 4.1 21 TYPICAL SIGNAL LATENCY OPERATING MODE TEST CONDITIONS LATENCY INPUT OUTPUT DIGITAL CORE AIF to DAC Stereo Path Digital input (AIFn) to analogue output (HPOUT). Signal is routed via the digital core ASRC function in the asynchronous test cases only. fs = 48kHz fs = 48kHz Synchronous 358µs fs = 44.1kHz fs = 44.1kHz Synchronous 391µs fs = 16kHz fs = 16kHz Synchronous 720µs fs = 8kHz fs = 8kHz Synchronous 1428µs fs = 8kHz fs = 44.1kHz Asynchronous 1940µs fs = 16kHz fs = 44.1kHz Asynchronous 1240µs DMIC to AIF Stereo Path Digital input (INn) to digital output (AIFn). Digital core High Pass filter included in signal path. fs = 48kHz fs = 48kHz Synchronous 236µs fs = 44.1kHz fs = 44.1kHz Synchronous 260µs fs = 16kHz fs = 16kHz Synchronous 732µs fs = 8kHz fs = 8kHz Synchronous 1543µs |
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