CS47L24 datasheet(22/256 Pages) CIRRUS

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CS47L24

Rev 4.1

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK & FREQUENCY LOCKED LOOP (FLL)

MCLK

tMCLKL

tMCLKH

tMCLKY

VIH

VIL

Figure 1 Master Clock Timing

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Master Clock Timing (MCLK1, MCLK2)

MCLK cycle time

MCLK as input to FLL,

FLLn_REFCLK_DIV=00

MCLK as input to FLL,

FLLn_REFCLK_DIV=01

MCLK as input to FLL,

FLLn_REFCLK_DIV=10

MCLK as input to FLL,

FLLn_REFCLK_DIV=11

12.5

MCLK as direct SYSCLK or

ASYNCCLK source

MCLK duty cycle

MCLK as input to FLL

80:20

20:80

MCLK as direct SYSCLK or

ASYNCCLK source

60:40

40:60

Frequency Locked Loops (FLL1, FLL2)

FLL input frequency

FLLn_REFCLK_DIV=00

0.032

13.5

MHz

FLLn_REFCLK_DIV=01

0.064

FLLn_REFCLK_DIV=10

0.128

FLLn_REFCLK_DIV=11

0.256

FLL synchroniser input

frequency

FLLn_SYNCCLK_DIV=00

0.032

13.5

MHz

FLLn_SYNCCLK_DIV=01

0.064

FLLn_SYNCCLK_DIV=10

0.128

FLLn_SYNCCLK_DIV=11

0.256

CS47L24 Datasheet(PDF) 22 Page - Cirrus Logic

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