CS47L24 datasheet(88/256 Pages) CIRRUS

88 / 256 page

CS47L24

Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3811

(0EE3h)

ASRC_RA

TE2

14:11

ASRC_RATE2

[3:0]

1000

ASRC Sample Rate select for

ASYNCCLK domain

1000 = ASYNC_SAMPLE_RATE_1

1001 = ASYNC_SAMPLE_RATE_2

All other codes are Reserved.

The selected sample rate is valid in the

range 8kHz to 48kHz.

The ASRC_IN2L_SRC and

ASRC_IN2R_SRC registers should be set

to 00h before ASRC_RATE2.

Table 22 Digital Core ASRC Control

ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC)

The CS47L24 supports multiple signal paths through the digital core. The Isochronous Sample Rate Converters (ISRCs)

provide sample rate conversion between synchronised sample rates on the SYSCLK clock domain, or between

synchronised sample rates on the ASYNCCLK clock domain.

There are three Isochronous Sample Rate Converters (ISRCs). Each of these provides four signal paths between two

different sample rates, as illustrated in Figure 29.

The sample rates associated with each ISRC can be set independently. Note that the two sample rates associated with

any single ISRC must both be referenced to the same clock domain (SYSCLK or ASYNCCLK).

When an ISRC is used on the SYSCLK domain, then the associated sample rates may be selected from

SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3.

When an ISRC is used on the ASYNCCLK domain, then the associated sample rates are ASYNC_SAMPLE_RATE_1

and ASYNC_SAMPLE_RATE_2.

See “Clocking and Sample Rates” for details of the sample rate control registers.

Each ISRC supports sample rates in the range 8kHz to 192kHz. The higher of the sample rates associated with each

ISRC must be an integer multiple of the lower sample rate; all possible integer ratios are supported (i.e., up to 24).

Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where

‘n’ identifies the applicable ISRC 1, 2 or 3). Note that, in each case, the higher of the two sample rates must be selected

by ISRCn_FSH.

The ISRCn_FSL and ISRCn_FSH registers should not be changed if any of the respective *_SRCn registers is non-zero.

The associated *_SRCn registers should be cleared to 00h before writing new values to ISRCn_FSL or ISRCn_FSH. A

minimum delay of 125µs should be allowed between clearing the *_SRCn registers and writing to the associated

ISRCn_FSL or ISRCn_FSH registers. See Table 23 for further details.

e ISRCn ‘interpolation’ paths (increasing sample rate) are enabled using the ISRCn_INT1_ENA, ISRCn_INT2_ENA,

ISRCn_INT3_ENA and ISRCn_INT4_ENA register bits.

The ISRCn ‘decimation’ paths (decreasing sample rate) are enabled using the ISRCn_DEC1_ENA, ISRCn_DEC2_ENA,

ISRCn_DEC3_ENA and ISRCn_DEC4_ENA register bits.

A notch filter is provided in each of the ISRC paths; these are enabled using the ISRCn_NOTCH_ENA bits. The filter is

configured automatically according to the applicable sample rate(s). It is recommended to enable the filter for typical

applications. Disabling the filter will provide maximum ‘pass’ bandwidth, at the expense of degraded stopband

attenuation.

The CS47L24 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the

commanded ISRC and digital mixing functions. If an attempt is made to enable an ISRC signal path, and there are

insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are

already active will not be affected under these circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose

Input / Output

” and “Interrupts” for further details.

The status bits in Registers R1600 to R3000 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

CS47L24 Datasheet(PDF) 88 Page - Cirrus Logic

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