UPD78044F datasheet(49/90 Pages) NEC

49 / 90 page

µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)

Data Sheet U16369EJ1V0DS

Subsystem Clock Oscillator Characteristics (TA = –40 to +85

°C, VDD = 1.8 to 5.5 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Crystal

Oscillation

32.768

kHz

resonator

frequency (fXT)Note 1

Oscillation

4.0 V

≤ VDD ≤ 5.5 V

1.2

stabilization timeNote 2

1.8 V

≤ VDD < 4.0 V

External

X1 input

38.5

kHz

clock

frequency (fXT)Note 1

X1 input high-/low-level

µs

width (tXTH, tXTL)

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor to the same potential as VSS1.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

Remark

For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

XT2

XT1VPP

XT1

XT2

UPD78044F Datasheet(PDF) 49 Page - NEC

UPD78044F Datasheet(HTML) 49 Page - NEC

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