UPD78044F datasheet(14/90 Pages) NEC

14 / 90 page

µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)

Data Sheet U16369EJ1V0DS

3.1 Port Pins (2/2)

Pin Name

I/O

Function

After Reset

Alternate

Function

P70

I/O

Port 7

Input

TI00/TO0

P71

6-bit I/O port.

TI01

P72

Input/output can be specified in 1-bit units.

TI50/TO50

P73

An on-chip pull-up resistor can be specified by software.

TI51/TO51

P74

PCL

P75

BUZ

3.2 Non-Port Pins (1/2)

Pin Name

I/O

Function

After Reset

Alternate

Function

INTP0

Input

External interrupt request input by which the valid edge (rising edge,

Input

P00

INTP1

falling edge, or both rising and falling edges) can be specified.

P01

INTP2

P02

INTP3

P03/ADTRG

SI30

Input

Serial interface serial data input.

Input

P20

SI31Note 1

P34

SDA0Note 2

I/O

Serial interface serial data input/output

Input

P32

SO30

Output

Serial interface serial data output.

Input

P21

SO31Note 1

P35

SCK30

I/O

Serial interface serial clock input/output.

Input

P22

SCK31Note 1

P36

SCL0Note 2

P33

RxD0

Input

Serial data input for asynchronous serial interface.

Input

P23

TxD0

Output

Serial data output for asynchronous serial interface.

Input

P24

ASCK0

Input

Serial clock input for asynchronous serial interface.

Input

P25

TI00

Input

External count clock input to 16-bit timer/event counter 0.

Input

P70/TO0

Capture trigger signal input to capture register 01 (CR01) of 16-bit timer/

event counter 0.

TI01

Capture trigger signal input to capture register 00 (CR00) of 16-bit timer/

P71

event counter 0.

TI50

External count clock input to 8-bit timer/event counter 50.

P72/TO50

TI51

External count clock input to 8-bit timer/event counter 51.

P73/TO51

TO0

Output

16-bit timer/event counter 0 output.

Input

P70/TI00

TO50

8-bit timer/event counter 50 output (shared with 8-bit PWM output).

Input

P72/TI50

TO51

8-bit timer/event counter 51 output (shared with 8-bit PWM output).

P73/TI51

PCL

Output

Clock output (for trimming of main system clock and subsystem clock).

Input

P74

BUZ

Output

Buzzer output.

Input

P75

AD0 to AD7

I/O

Lower address/data bus for extending memory externally.

Input

P40 to P47

Notes 1.

SI31, SO31, and SCK31 are incorporated only in the

µPD78F0034B and 78F0034B(A).

SDA0 and SCL0 are incorporated only in the

µPD78F0034BY and 78F0034BY(A).

UPD78044F Datasheet(PDF) 14 Page - NEC

UPD78044F Datasheet(HTML) 14 Page - NEC

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