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TAS2764YBHT Datasheet(PDF) 40 Page - Texas Instruments |
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TAS2764YBHT Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 107 page  Table 8-15. TDM Configuration 0 Field Descriptions (continued) Bit Field Type Reset Description 5 RAMP_RATE RW 0h Sample rate based on 44.1kHz or 48kHz when CLASSD_SYNC=1. 0b = 48kHz 1b = 44.1kHz 4 AUTO_RATE RW 0h Auto detection of TDM sample rate. 0b = Enabled 1b = Disabled 3-1 SAMP_RATE[2:0] RW 4h Sample rate of the TDM bus. 000b-011b = Reserved 100b = 44.1/48 kHz 101b = 88.2/96 kHz 110b-111b = Reserved 0 FRAME_START RW 1h TDM frame start polarity. 0b = Low to High on FSYNC 1b = High to Low on FSYNC 8.9.14 TDM_CFG1 (page=0x00 address=0x09) [reset=02h] Sets TDM RX justification, offset and capture edge. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-16. TDM Configuration 1 Field Descriptions Bit Field Type Reset Description 7 Reserved R 0h Reserved 6 RX_JUSTIFY RW 0h TDM RX sample justification within the time slot. 0b = Left 1b = Right 5-1 RX_OFFSET[4:0] RW 1h TDM RX start of frame to time slot 0 offset (SBCLK cycles). 0 RX_EDGE RW 0h TDM RX capture clock polarity. 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK 8.9.15 TDM_CFG2 (page=0x00 address=0x0A) [reset=0Ah] Sets TDM RX time slot select, word length and time slot length. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-17. TDM Configuration 2 Field Descriptions Bit Field Type Reset Description 7-6 IVMON_LEN[1:0] RW 0h Sets the current and voltage data to length of 00b = 16 bits 01b = 12 bits 10b = 8 bits 11b = Reserved 5-4 RX_SCFG[1:0] RW 0h TDM RX time slot select config. 00b = Mono with time slot equal to I2C address offset 01b = Mono left channel 10b = Mono right channel 11b = Stereo downmix (L+R)/2 3-2 RX_WLEN[1:0] RW 2h TDM RX word length. 00b = 16-bits 01b = 20-bits 10b = 24-bits 11b = 32-bits TAS2764 SLOS998 – DECEMBER 2020 www.ti.com 40 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TAS2764 |
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