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TAS2764YBHT Datasheet(PDF) 12 Page - Texas Instruments |
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TAS2764YBHT Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 107 page  TA = 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs(unless otherwise noted) MIN NOM MAX UNIT tSU(FSYNC) FSYNC setup time 8 ns tHLD(FSYNC) FSYNC hold time 8 ns tSU(SDIN/ICC) SDIN/ICC setup time 8 ns tHLD(SDIN/ICC) SDIN/ICC hold time 8 ns td(SBCLK_SDOUT/ICC) SBCLK to SDOUT/ICC delay 50% of SBCLK to 50% of SDOUT/ICC, IOVDD=1.8V 13 ns 50% of SBCLK to 50% of SDOUT/ICC, IOVDD=1.2V 17 tr(SBCLK) SBCLK rise time 10 % - 90 % Rise Time 8 ns tf(SBCLK) SBCLK fall time 90 % - 10 % Fall Time 8 ns 6.8 tBUF STO STA th(STA) tLOW tr th(DAT) tf tHIGH tsu(DAT) SDA SCL tsu(STA) STA th(STA) STO tsu(STO) Figure 6-1. I2C Timing Diagram Figure 6-2. TDM and ICC Timing Diagram TAS2764 SLOS998 – DECEMBER 2020 www.ti.com 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TAS2764 |
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