| Electronic Components Datasheet Search |
|
VSC8221 Datasheet(PDF) 48 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
VSC8221 Datasheet(HTML) 48 Page - Microsemi Corporation |
|
48 / 138 page ![]() VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 48 of 48 48 15.2 Low-Power State in the low-power state, all major digital blocks are powered down. However the following functionality is provided: • SMi interface (MDC/MODDEF1, MDiO/MODDEF2, MDiNT) • CLKOUT and CLKOUTMiCRO in this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of the low power state and transitions to the Normal operating state when signal energy is detected on the media. This happens when the PHY is connected to one of the following: • Auto-negotiation capable link partner • Auto-negotiation incapable (blind/forced) 100BTX only link partner • Auto-negotiation incapable (blind/forced) 10BT only link partner • Another PHY in enhanced ActiPHY LP wakeup state in the absence of signal energy on the media pins, the PHY will transition from the low power state to the LP Wake up state periodically based on the programmable sleep timer. Two register bits (Mii Register bits 28.1:0) are provided to program the value of the sleep timer. The sleep timer can be programmed to 2'b00 (1sec), 2'b01 (2sec), 2'b10 (3sec), or 2'b11 (4sec). The default value is 2 seconds. The actual sleep time duration is randomized by -80ms to +60ms to prevent two PHYs in Enhanced ActiPHY mode from entering a lock-up state. 15.3 LP Wake-Up State in this state, the PHY attempts to wake up the link partner. One complete FLP (Fast link Pulse) is sent on both pairs A and B of the CAT5 media. in this state, the following functionality is provided: • SMi interface (MDC/MODDEF1, MDiO/MODDEF2, MDiNT) • CLKOUT and CLKOUTMiCRO After sending signal energy on the relevant media, the PHY returns to the Low power state. 15.4 Normal Operating State in this state, the PHY establishes a link with a link partner. When the media is unplugged or the link partner is powered down, the PHY waits for the duration programmed through a link status timeout timer and then enters the low power state. The Link Status Timeout timer can be programmed to 2'b00 (1sec), 2'b01 (2sec), 2'b10 (3sec) or 2'b11 (4sec). The default value for this timer is 2 seconds. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |