VSC8221 datasheet(95/138 Pages) MICROSEMI

95 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

95 of 106

106

28.12 – CD Pair Swap1

When bit 28.12 returns a “1”, the PHY has determined that subchannel cable pairs C and D have been swapped between the

far-end transmitted and the receiver. When bit 28.12 returns a “1”, the PHY internally swaps pairs C and D (as long as bit 18.5 is

set to “0”).1

28.11 – A Polarity inversion

When bit 28.11 returns a “1”, the PHY has determined that the polarity of subchannel cable pair A has been inverted between

the far-end transmitter and the near-end receiver. When bit 28.11 returns a “1”, the PHY internally corrects the pair inversion.

Polarity-inversion correction runs in all three modes; as a result, the state of 28.11 is valid only when bit 1.5 is set to “1”.

28.10 – B Polarity inversion

When bit 28.10 returns a “1”, the PHY has determined that the polarity of subchannel cable pair B has been inverted between

the far-end transmitter and the near-end receiver. When bit 28.10 returns a “1”, the PHY internally corrects the pair inversion.

Polarity-inversion correction runs in all three modes; as a result, the state of 28.10 is valid only when bit 1.5 is set to “1”.

28.9 – C Polarity inversion2

When bit 28.9 returns a “1”, the PHY has determined that the polarity of subchannel cable pair C has been inverted between the

far-end transmitter and the near-end receiver. When bit 28.9 returns a “1”, the PHY internally corrects the pair inversion.

Polarity-inversion correction runs in all three modes; as a result, the state of 28.9 is valid only when bit 1.5 is set to “1”.

28.8 – D Polarity inversion1

When bit 28.8 returns a “1”, the PHY has determined that the polarity of subchannel cable pair D has been inverted between the

far-end transmitter and the near-end receiver. When bit 28.8 returns a “1”, the PHY internally corrects the pair inversion.

Polarity-inversion correction runs in all three modes; as a result, the state of 28.8 is valid only when bit 1.5 is set to “1”.

28.7 – Reserved

28.6 - Enable Enhanced ActiPHY Mode

When bit 28.6 is set to a “1”, the enhanced ActiPHY power management mode is set in the VSC8221. The reset value for this bit

is determined by the Enhanced ActiPHY bit in the CMODE hardware configuration.

28.5 – FDX Status

Bit 28.5 indicates the actual FDX/HDX operating mode of the PHY.

28.4:3 – Speed Status

Bits 27.4:3 indicate the actual operating speed of the PHY.

28.2 – Reserved

This bit must always be set to ‘1’.

28.1:0 - Enhanced ActiPHYTM Sleep Timer

This sets the time period the PHY stays in ‘Low Power’ State when Enhanced ActiPHYTM mode is enabled, before entering the

‘LP Wake-up State’. Refer to Section 15 on page 47 for details.

1This bit applies only in 1000BASE-T mode.

2This bit applies only in 1000BASE-T mode.

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