VSC8221 datasheet(51/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

51 of 52

17 ADVANCED TEST MODES

17.1 Ethernet Packet Generator (EPG)

For system-level debugging and in-system production testing, the VSC8221 includes an Ethernet packet generator. This can be

used to isolate problems between the MAC and PHY and between a local PHY and remote link partner. it is intended for use

with lab testing equipment or in-system test equipment only, and should not be used when the VSC8221 is connected to a live

network.

To use the EPG, it must be enabled by writing a “1” to Mii Register 29E.15. This effectively disables all MAC-interface transmit

pins and selects the EPG as the source for all data transmitted onto the VSC8221 media interface. For this reason, packet loss

will occur if the EPG is enabled during transmission of packets from MAC to PHY. The MAC receive pins will still be active when

the EPG is enabled, however. if it is necessary to disable the MAC receive pins as well, this can be done by writing a “1” to MII

When a “1” is written to MII Register Bit 29E.14, the VSC8221 will begin transmitting iEEE802.3 layer-2 compliant packets with

a data pattern of repeating 16-bit words as specified in MII Register 30E. The source and destination addresses for each

packet, packet size, interpacket gap, FCS state and transmit duration can all be controlled through Mii Register 29E. Note that if

MII Register Bit 29E.13 is cleared, MII Register Bit 29E.14 will be cleared automatically after 30,000,000 packets have been

transmitted.

17.2 CRC Counter

When the EPG is enabled, a bad-CRC counter is also available for all incoming packets. This counter is available in MII

17.3 Far-End Loopback

Far-end loopback mode, when enabled (Mii Register bit 23.3 = 1), forces incoming data from a link partner on the media

interface to be retransmitted back to the link partner on the media interface as shown in the figure below. in addition, the

incoming data will also appear on the receive data pins (RDP/RDN) of the MAC interface. Data present on the transmit pins of

the MAC interface are ignored in this mode. For more information, please refer to MII Register 23 (Extended PHY Control

Figure 18. Far-end Loopback Block Diagram

Link Partner

VSC8221

Serial

MAC

RDP/RDN

TDP/TDN

CAT-5 or Fiber

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