VSC8221 datasheet(99/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

99 of 106

106

17E.15:5 - Reserved

17E.4:2 - RDP/RDN SCLKP/SCLKN Output Swing Control

These bits set the output swing amplitude (peak-to-peak voltage) on the RDP/RDN SCLKP/SCKLN Output Swing output pins.

17E.1 - 25mv Hysteresis Disable

When set, this bit disables the 25mv Hysteresis built into the TDP/TDN and SDiP/SDiN high speed differential input pins.

17E.0 - CLKOUTMiCRO Enable

When set, the CLKOUTMiCRO clock output is enabled.

23.3.3 Register 18E (12h) - Reserved

18E.15:0 - Reserved

23.3.4 Register 19E (13h) - SerDes Control # 2

19E.15:2 - Reserved

19E.1 - SiGDET Pin Direction

This bit is valid in non-SFP modes i.e. when Mii Register 21E.15 is clear. in non-SFP mode, the RXLOS/SiGDET pin behaves

like the SiGDET pin. When set as an input, the assertion of the SiGDET pin enables the SerDes block in Serial MAC to CAT5

category of PHY operating modes. When set as an output in Serial MAC to CAT5 Media operating modes, the SiGDET pin is

asserted when the CAT5 Media link is up. in Fiber Media operating modes, the SiGDET output is asserted if the PHY sees valid

8B/10B encoded signals on the TDP/TDN pins.

19E.0 - SiGDET Pin Polarity

This bits sets the assertion polarity of the SiGDET pins. This bit is valid in both cases i.e when SiGDET is an input or an output.

Bit

Name

Access

States

Reset Value

Sticky

15:0

Reserved

00000001 11111111

Bit

Name

Access

States

Reset Value

Sticky

15:2

Reserved

00000000 00000000

SiGDET Pin Direction

R/W

0 = input

1 = Output

CMODE

SiGDET Pin Polarity

R/W

0 = Active High

1 = Active Low

VSC8221 Datasheet(PDF) 99 Page - Microsemi Corporation

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