ADAV803ASTZ datasheet(36/56 Pages) AD

36 / 56 page

ADAV803

Rev. 0 | Page 36 of 56

RES

RxBCONF4

NF3

RxB

RxBCONF0

Table 26. Receiver Buffer Configuration Register

RES

RxBCON

RxBCO

CONF2–1

2, 1

ADDRESS = 0001011 (0x0B)

RxBCONF5

If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit

enabled only when there is a change in the start (ID) bit.

interrupt is

0 = User bit interrupt is enabled in normal mode.

If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.

termines whether Channel A and Channel B user bits are stored in the buffer together or separated

and B.

eceiver channel status is read, which is 192 audio frames.

of the receiver channel status block changes from the previous channel

IEC60958-3 standard.

xBCONF0

Defines the user bit buffer size, if RxBCONF2–1 = 01.

rt of the buffer.

1 =

RxBCONF4

This bit de

between A

0 = User bits are stored together.

1 = User bits are stored separately.

RxBCONF3

Defines the function of RxCSBINT.

0 = RxCSBINT are set when a new block of r

1 = RxCSBINT is set only if the first five bytes

status block.

RxBCONF2–1

Defines the user bit buffer.

e ignored.

00 = User bits ar

01 = Updates the second user bit buffer when the first user bit buffer is full.

10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If the

PRO bit is not set, formats the user bits according to the

11 = Reserved.

0 = 384 bits with Preamble Z as the sta

8 b

h Pr

1 = 76

its wit

eamble Z as the

rt of the buffer.

Table 27. Transmitter Control Register

RES

TxVALIDITY

TxRATIO2–0

TxCLKSEL1–0

TxENABLE

5, 4, 3

2, 1

ADDRESS = 0001100 (0x0C)

TxVALIDITY

This bit is used to set or clear the VALIDITY bit in the AES3/SPDIF transmit stream.

0 = Audio is suitable for D/A conversion.

1 = Audio is not suitable for D/A conversion.

TxRATIO2–0

Determines the AES3/SPDIF transmitter to AES3/SPDIF receiver ratio.

00 = Internal Clock 1 is the cl

01 = Internal Clock 2 is the clock source for the transmitter.

ce for the transmitter.

3/SPDIF transmitter is disabled.

000 = Transmitter to receiver ratio is 1:1.

001 = Transmitter to receiver ratio is 1:2.

010 = Transmitter to receiver ratio is 1:4.

101 = Transmitter to receiver ratio is 2:1.

110 = Transmitter to receiver ratio is 4:1.

TxCLKSEL1–0

Selects the clock source for the AES3/SPDIF transmitter.

ock source for the transmitter.

10 = Recovered PLL clock is the clock sour

11 = Reserved.

TxENABLE

Enables the AES3/SPDIF transmitter.

0 = AES

1 = AES3/SPDIF transmitter is enabled.

ADAV803ASTZ Datasheet(PDF) 36 Page - Analog Devices

ADAV803ASTZ Datasheet(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL