ADAV803ASTZ datasheet(39/56 Pages) AD

39 / 56 page

ADAV803

Rev. 0 | Page 39 of 56

d Only)

PRE_C07–PRE_C00

Table 36. Preamble-C LSB Register (Rea

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010101 (0x15)

PRE_C07–00

Eight least signif

nt bits of th

-bit Preamb -C, when nonaudio data is detected according to the IEC60937

d; otherwise, bits show zeros.

ica

e 16

standar

Table 37. Preamble-D M

SB Register (Read Only)

E_D15–PRE_D08

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010110 (0x16)

PRE_D15–08

nonaudio data is detected according to the IEC60937

nonaudio is used, this becomes the eight most significant bits

ght most significant bits of the 16-bit Preamble-D, when

andard; otherwise, bits show zeros. When subframe

the 16-bit Preamble-C of Channel B.

Table 38. Preamble-D LSB Register (Read Only)

PRE_D07–PRE_D00

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010111 (0x17)

PRE_D07–00

mble-D, when nonaudio data is detected according to the IEC60937

standard; otherwise, bits

becomes the eight most significant bits

ght least significant bits of the 16-bit Prea

show zeros. When subframe nonaudio is used, this

the 16-bit Preamble-C of Channel B.

Table 39. Receiver Erro

amble

CRCError

NoStream

BiPhase/ Parity

Lock

r Register (Read Only)

Validity

Emphasis

NonAudio

Pre

NonAudio

ADDRESS = 0011000 (0x18)

RxValidity

ived stream.

is is the VALIDITY bit in the AES3 rece

Emphasis

This bit is set, if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an

interrupt unless it changes state.

onaudio) is set. Once it has been read, it does not generate another

upt unle

data bec

audio or

pe of no

nAudio

is bit is set,

e audio da

s nonaudio due to the det

ion of a pream

. The nonau

preamble type register

s what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt

ster

NonAudio

This bit is set, when Channel Status Bit 1 (n

interr

ss the

omes

the ty

naudio data c

nges.

Preamble

indicate

if th

ta i

ect

ble

dio

unless it changes state.

This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error regi

CRCError

is read.

This bit is set, if there is no AES3/SPDIF stream present at the AES3/SPDIF receiver. Once read, it remains high and

NoStream

does not generate an interrupt unless it changes state.

This bit is set, if a biphase or parity error occurred in the AES3/SPDIF stream. This bit is not cleared until the register is

BiPhase/Parity

read.

This bit is set, if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not

generate an interrupt unless it changes state.

Lock

ADAV803ASTZ Datasheet(PDF) 39 Page - Analog Devices

ADAV803ASTZ Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL