ADAV803ASTZ datasheet(52/56 Pages) AD

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ADAV803

Rev. 0 | Page 52 of 56

PLL2_Source

RES

Table 77. PLL Clock Source Regist

PLL1_Sour

RES

ADDRESS = 1111000 (0x78)

PLL1_Source

Selects the clock source for PLL1.

0 = XIN.

1 = MCLKI.

PLL2_Source

ck source for PLL2.

Selects the clo

0 = XIN.

1 = MCLKI.

Table 78. PLL Output

RES

DIRINPD

DIRIN_PIN

RES

SYSCLK1

SYSCLK2

SYSCLK3

Enable

RES

ADDRESS = 1111010 (0x7A)

DIRINPD

This bit powers down the SPDIF receiver.

0 = Normal.

1 = Power-down.

DIRIN_PIN

This bit determines the input levels of the DIRIN pin.

down to 200 mV according to AES3 requirements.

ons section.

YSCLK1

YSCLK2

LK2 output.

0 = Enabled.

YSCLK3

es the SYSCLK3 ou

Enabled.

bled.

0 = DIRIN accepts input signals

1 = DIRIN accepts input signals as defined in the Specificati

Enables the SYSCLK1 output.

0 = Enabled.

1 = Disabled.

Enables the SYSC

1 = Disabled.

Enabl

tput.

0 =

1 = Disa

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