ADAV803ASTZ datasheet(41/56 Pages) AD

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ADAV803

Rev. 0 | Page 41 of 56

sk Register

RES

OVRL Mask

Table 42. Sample Rate Converter Error Ma

RES

OVRR Ma

MUT

IND MASK

ADDRESS = 0011011 (0x1B)

OVRL Mask

Masks the OVRL from generating an interrupt.

0 = OVRL bit does not generate an interrupt.

1 = OVRL bit generates an interrupt.

OVRR Mask

Masks the OVRR from generating an interrupt.

ASK

interrupt.

0 = OVRR bit does not generate an interrupt.

1 = OVRR bit generates an interrupt. Reserved.

MUTE_IND M

Masks the MUTE_IND from generating an

0 = MUTE_IND bit does not generate an interrupt.

1 = MUTE_IND bit generates an interrupt.

Table 43. Interrupt St

TxCSINT

RxCSDIFF

RxUBINT

RxCSBINT

RxERROR

atus Register

SRCError

TxCSTINT

TxUBINT

ADDRESS = 0011100 (0x1C)

SRCError

This bit is set, if one of the sample rate converter interrupts is asserted, and the host should immediately read the

gh until the interrupt status register is read.

sample rate converter error register. This bit remains hi

TxCSTINT

This bit is set, if a write to the transmitter channel status buffer was made while transmitter channel status bits were

fer to the SPDIF transmit buffer.

his bit remains high until the interrupt status register is read.

it buffer has transmitted its block of channel status. This bit remains

ceiver Channel Status B clock. This bit

remains high until read, but does not generate an interrupt.

eiver user bit buffer has a new block or message. This bit remains high until the interrupt

RxCSBIN

it is set, if

block of c

tus is rea

0, or if the

when

BCONF3 = 1.

is bit remains

gh until the interrupt status register is read.

is set, if one of the AES3/SPDIF receiver interrupts is asserted, and the host should immediately read the

ins high until the interrupt status register is read.

being copied from the transmitter CS buf

TxUBINT

This bit is set, if the SPDIF transmit buffer is empty. T

TxCSINT

This bit is set, if the transmitter channel status b

high until the interrupt status register is read.

This bit is set, if the receiver Channel Status A block is different from the re

RxCSDIFF

RxUBINT

This bit is set, if the rec

status register is read.

This b

a new

hannel sta

d when RxBC NF3 =

channel status ha changed

RxERROR

This bit

receiver error register. This bit rema

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