ADAV803ASTZ datasheet(48/56 Pages) AD

48 / 56 page

ADAV803

Rev. 0 | Page 48 of 56

Gain Register

Table 66. ADC Right Channel PGA

RES

AGR5

AGR4

AGR3

AGR2

AGR1

AGR0

ADDRESS = 1101101 (0x6D)

AGR5–0

PGA right channel gain control.

000000 = 0 dB.

000001 = 0.5 dB.

…

101111 = 23.5 dB.

110000 = 24 dB.

…

111111 = 24 dB.

Table 67. ADC Control Register 1

AMC

HPF

PWRDWN

ANA_PD

MUTER

MUTEL

PLPD

PRPD

ADDRESS = 1101110 (0x6E)

AMC

ADC modulator clock.

0 = ADC MCLK/2 (128 × fS).

1 = ADC MCLK/4 (64 × fS).

HPF

1 = HPF enabled.

wer-down.

UTER

Mute ADC right channel.

ormal.

Po er-dow

ht power-down.

High-pass filter enable.

0 = Normal.

PWRDWN

ADC power-down.

0 = Norma

1 = Power-d

ion po

ANA_PD

ADC analog sect

0 = Normal.

1 = Power-down.

0 = Normal.

1 = Muted.

MUTEL

Mute ADC left channel.

0 = Normal.

1 = Muted.

PLPD

PGA left power-down.

0 = N

1 =

PRPD

PGA rig

0 = Normal.

1 = Power-down.

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