VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-68
Graphics Accelerator PCI Bus Master Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Port 2287-2284 – MC Command Queue .........................RW
31-12 Page Table Address
11
SP Command Present
0
SP Command is Absent ..........................default
1
SP Command is Present
10-9 Video Output Display Fields
00 -reserved-................................................default
01 Top
10 Bottom
11 Both
8-6
Video Output Display Buffer
000 F0
.....................................................default
001 F1
010 F2
011 F3
100 H0
101 H1
110 H2
111 -reserved-
5-4
MC Buffer 2
Bit-1 = 1
Bit-1 = 0
00
H0
top
01
H1
bottom
10
H2
both
11 No Buf 2
n/a
3-2
MC Buffer 1
Bit-1 = 1
Bit-1 = 0
00
H0
F0
01
H1
F1
10
H2
F2
11
n/a
F3
1
MC Buffer is Field
0
Not Field ................................................default
1
Field
0
MC Command in Queue
0
Disable ...................................................default
1Enable
This register changes definition when written with bit-0 = 1.
This address then becomes “MC Status” with the definition of
the bits matching the following bit definitions until MC-Status
bit-0 is cleared by hardware.
Port 2285-2284 – MC Status............................................ RW
15
Task Pop Out Done Status
14-12 FIFO Status
11
MC Decode Done Status
10-9 Video Output Display Fields
00 -reserved- ............................................... default
01 Top
10 Bottom
11 Both
8-6
Video Output Display Buffer
000 F0
.................................................... default
001 F1
010 F2
011 F3
100 H0
101 H1
110 H2
111 -reserved-
5-4
MC Buffer 2
Bit-1 = 1
Bit-1 = 0
00
H0
top
01
H1
bottom
10
H2
both
11 No Buf 2
n/a
3-2
MC Buffer 1
Bit-1 = 1
Bit-1 = 0
00
H0
F0
01
H1
F1
10
H2
F2
11
n/a
F3
1
MC Buffer is Field
0
Not Field ................................................ default
1
Field
0
MC Status
0
Not in progress....................................... default
1In Progress
The bit definitions above are valid only when bit-0 is equal to
1. When hardware clears bit-0, bit definitions revert to those
defined by the “MC Command Queue” register defined in the
left hand column of this page.
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