P5021 datasheet(110/155 Pages) NXP

110 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

110

This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are

specified at the component pins.

Powered down DC input impedance

ZRX-HIGH-IMP-DC

50 k

—

Required receiver D+ as well as D–

DC Impedance when the receiver

terminations do not have power.

See Note 3.

Electrical idle detect threshold

VRX-IDLE-DET-DIFFp-p

—

175

VRX-IDLE-DET-DIFFp-p =

× |V

RX-D+ – VRX-D–|

Measured at the package pins of the

receiver

Notes:

1. Measured at the package pins with a test load of 50

Ω to GND on each pin.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the receiver ground.

Table 65. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (XVDD = 1.5V or 1.8V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max Units

Notes

Differential input peak-to-peak voltage

VRX-DIFFp-p

120

—

1200

VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|

See Note 1.

DC differential input impedance

ZRX-DIFF-DC

100

120

Receiver DC Differential mode

impedance. See Note 2

DC input impedance

ZRX-DC

Required receiver D+ as well as D–

DC Impedance (50 ±20%

tolerance). See Notes 1 and 2.

Powered down DC input impedance

ZRX-HIGH-IMP-DC

—

Ω Required receiver D+ as well as D–