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AD5413

Data Sheet

Rev. 0 | Page 8 of 49

TIMING CHARACTERISTICS

AVDD1 = +15 V, AVDD2 = +5 V, AVSS = −15 V, VLOGIC = +1.71 V to +5.5 V, AGND = DGND = REFGND = 0 V, REFIN = +2.5 V external,

RLOAD = 1 kΩ and CLOAD = 220 pF for voltage output, and RLOAD = 300 Ω for current output. All specifications at TA = −40°C to +105°C,

TJ < 125°C, unless otherwise noted.

Table 3.

Parameter1, 2, 3

1.71 V ≤ VLOGIC < 3 V

3 V ≤ VLOGIC ≤ 5.5 V

Unit

Test Conditions/Comments

ns minimum

SCLK cycle time, write operation

120

ns minimum

SCLK cycle time, read operation

ns minimum

SCLK high time, write operation

ns minimum

SCLK high time, read operation

ns minimum

SCLK low time, write operation

ns minimum

SCLK low time, read operation

ns minimum

SYNC falling edge to SCLK falling edge setup time,

write operation

ns minimum

SYNC falling edge to SCLK falling edge setup time,

read operation

ns minimum

24th or 32nd SCLK falling edge to SYNC rising edge

500

ns minimum

SYNC high time (applies to all register writes outside

of those listed in this table)

1.5

μs minimum

SYNC high time (DAC_INPUT register write)

500

μs minimum

SYNC high time (DAC_CONFIG register write, where the

RANGE bits (Bits[3:0]) change, see the Calibration

Memory CRC section for more timing information)

ns minimum

Data setup time

ns minimum

Data hold time

750

ns minimum

LDAC falling edge to SYNC rising edge

t10

1.5

μs minimum

SYNC rising edge to LDAC falling edge

t11

250

ns minimum

LDAC pulse width low

t12

600

maximum

LDAC falling edge to DAC output response time, digital

slew rate control disabled

μs

maximum

LDAC falling edge to DAC output response time, digital

slew rate control enabled

t13

See the AC Performance

Characteristics section

See the AC Performance

Characteristics section

μs

maximum

DAC output settling time

t14

1.5

μs

maximum

SYNC rising edge to DAC output response time

(LDAC = 0)

t15

μs minimum

RESET pulse width low

t16

maximum

SCLK rising edge to SDO valid

t17

100

μs minimum

RESET rising edge to first SCLK falling edge after SYNC

falling edge

1 Guaranteed by design and characterization. Not production tested.

2 All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V.

3 See Figure 2 to Figure 5.

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