FS32K148HEX0MLFT datasheet(19/101 Pages) NXP

19 / 101 page

Table 10. Clock configuration (continued)

S32K1xx

S32K14xW

FLASH_CLK

28 MHz

VLPR mode

Clock source

SIRC

SYS_CLK/CORE_CLK

4 MHz

1 MHz

BUS_CLK

4 MHz

1 MHz

FLASH_CLK

1 MHz

0.25

STOP1/STOP2 mode

Clock source

FIRC

SYS_CLK/CORE_CLK

48 MHz

BUS_CLK

48 MHz

FLASH_CLK

24 MHz

16 MHz

VLPS mode

All clock source disabled 1

• For S32K11x – FIRC/SOSC

• For S32K14x, S32K14xW – FIRC/SOSC/SPLL

Table 11. Power mode transition operating behaviors for S32K1xx series

Symbol

Description

Min.

Typ.

Max.

Unit

tPOR

After a POR event, amount of time from the point VDD

reaches 2.7 V to execution of the first instruction

across the operating temperature range of the chip.

—

325

—

μs

VLPS → RUN

—

μs

STOP1 → RUN

0.07

0.075

0.08

μs

STOP2 → RUN

0.07

0.075

0.08

μs

VLPR → RUN

—

μs

VLPR → VLPS

5.1

5.7

6.5

μs

VLPS → VLPR

18.8

27.75

μs

RUN → Compute operation

0.72

0.75

0.77

μs

HSRUN → Compute operation

0.3

0.31

0.35

μs

RUN → STOP1

0.35

0.38

0.4

μs

RUN → STOP2

0.2

0.23

0.25

μs

RUN → VLPS

0.3

0.35

0.4

μs

RUN → VLPR

3.5

3.8

μs

VLPS → Asynchronous DMA Wakeup

105

110

125

μs

STOP1 → Asynchronous DMA Wakeup

1.1

1.3

μs

STOP2 → Asynchronous DMA Wakeup

1.1

1.3

μs

Pin reset → Code execution

—

214

—

μs

General

S32K1xx Data Sheet, Rev. 14, 08/2021

NXP Semiconductors

FS32K148HEX0MLFT Datasheet(PDF) 19 Page - NXP Semiconductors

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