FS32K148HEX0MLFT datasheet(56/101 Pages) NXP

56 / 101 page

Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and

are not tested in production.

For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference

supply quality should be better than SAR ADC. See application note AN5032 for details.

Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .

ADC conversion will become less reliable above maximum frequency.

When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.

Numbers based on the minimum sampling time of 275 ns.

For guidelines and examples of conversion rate calculation, see the Reference Manual section 'Calibration function'

Configuration used during the test to obtain this value is:

• VDD=VDDA=VREFH=2.5 V, 2.7 V, 3 V ,5.5 V, (externally forced)

• BUS CLK=48 MHz, ADC CLK=48MHz (FIRC Used), Calibration CLK=24MHz, Sample Time =14 Cyc, Averaging=32

• Resolution= 12 bit

• Conversion Mode: Continuous Conversion

• Channel: ADC0_SE1

• Temperatures: -40C, 25C, 135C

FS32K148HEX0MLFT Datasheet(PDF) 56 Page - NXP Semiconductors

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