WM8581 datasheet(53/94 Pages) WOLFSON

53 / 94 page

Product Preview

WM8581

PP Rev 1.0 March 2006

The recommended configuration sequences are as follows:

TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:

Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A,

PRESCALE_B, PLLB_N and PLLB_K for 32/44.1/48/88.2/96kHz (modes 2/3/4) S/PDIF

receiver sample rate operation.

Enable PLLA and PLLB by clearing the PLLAPD and PLLBPD bits.

Enable S/PDIF receiver by clearing the SPDIFRXPD and SPDIFPD bits.

Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF sample

frequency and clocking mode.

If indicated sample rate is 192kHz, write appropriate calculated values (relative to oscillator

frequency) to PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K (as appropriate) for

192kHz (mode 1) S/PDIF receiver sample rate operation.

TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR FROM

MODE 1 (192KHZ):

Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz (mode 1))

will be flagged to the application processor via the INT interrupt flag. The application processor must then

read the Interrupt Status Register. If the UPD_REC_FREQ flag is set, indicating that the clocking mode has

changed, proceed as follows:

Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF sample rate

frequency and clocking mode.

Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A,

PRESCALE_B, PLLB_N and PLLB_K based on indicated recovered S/PDIF sample

frequency and clocking mode.

This procedure is only strictly necessary when switching to or from 192kHz (mode 1) because the

PRESCALE_A,

PRESCALE_B,

PLLB_N

and

PLLB_K

values

are

the

same

for

32/44.1/48/88.2/96kHz (modes 2/3/4) sample rate operation. It is, however, good interrupt service

routine practice to write the appropriate PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K values

when every clocking mode change is detected.

PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE)

In hardware mode, the user has no access to the internal clocking control registers and hence a default

configuration is loaded at reset to provide maximum functionality.

The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL and

S/PDIF receiver control is fully automatic. All supported S/PDIF receiver sample rates can be used.

FREQMODE_x and POSTSCALE_x control is fully automatic to ensure that the MCLK output is maintained

at 256fs relative to the S/PDIF received sample rate.

In hardware mode, the OSCCLK must be 12MHz and hence the external crystal (or applied XIN clock) must

be 12MHz. No other OSCCLK frequencies are supported in hardware mode.

WM8581 Datasheet(PDF) 53 Page - Wolfson Microelectronics plc

WM8581 Datasheet(HTML) 53 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL