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XGS Datasheet(PDF) 19 Page - ON Semiconductor |
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XGS Datasheet(HTML) 19 Page - ON Semiconductor |
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19 / 53 page ![]() XGS Family www.onsemi.com 19 Table 7. POWER−UP SEQUENCE Symbol Definition Min Typ Max Unit t0 VDD_IO to VDD_PLL 0 (Note 5) 100 ms t1 VDD_PLL to VDD 0 (Note 5) 100 ms t2 VDD to VAA 0 (Note 5) 100 ms t3 VAA to VAA_PIX/VAA_PIX_BST/VAA_RD 0 (Note 5) 100 ms t4 VAA_PIX/VAA_PIX_BST/VAA_RD to VDD_SLVS 0 (Note 5) 100 ms tX EXTCLK Settling Time 0.5 30 (Note 4) ms t5 Hard Reset 30 EXTCLK cycles t6 Internal Initialization (ready once R0x3706 reads back 0xEB) 1.5 ms t7 PLL Lock Time 10 70 ms t8 Internal Initialization 6.5 ms 4. The EXTCLK settling time is component−dependent. 5. The minimum time does not include the settling time of the power supply. |
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