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of frames per context can be configured for each

context separately. In the example configuration

depicted in Figure 25, the sensor first generates three

frames using context 0 settings followed by a single

context 1 frame and two context 2 frames. The sensor

loops through this sequence until the sequencer is

disabled. The number of frames per context switch is

configured in contexts_reg.frames_ctxt0 (for context0).

3 x context 0

→ context 1 → 2 x context 2

→ 3 x context 0...

Context 0

Context 1

Context 2

Figure 25. Multiple Frame Context Switching

TEST PATTERN

The XGS sensor has the capability of injecting a number

of test patterns into the datapath. As the test pattern

generator is placed at the beginning âof the digital datapath,

it can be used to check the functions of the digital blocks or

to test the frame grabber or receiver operation. The test

patterns

can

configured

the

test_pattern_mode_reg.test_pattern_mode and only one

pattern can be activated at a given point in time.

DATA PEDESTAL

The data pedestal is a constant offset that is added to the

pixel values at the end of the datapath. The pedestal or offset

value can be configured separately for each color channel

(GR, GB, R and B) and for each context. The offset is a 12−bit

value.

GAIN STAGES

Analog Gain

A column−based analog gain of 1x, 2x or 4x can be

applied to the output signal.

Digital Gain

As opposed to the analog gain stage, the digital gain can

be configured to separate levels for each color channel (GR,

GB, R and B). The digital gain factor ranges from 1/32 to 2

in steps of 1/32 (64 steps) and its configuration can be

represented by the equation below:

Digital gain + Dg_factor 25

(eq. 1)

COMPANDING MODE

The companding mode can be used to compress 12−bit

pixel data into 10−bit values. The line time remains the time

required to convert a 12−bit ADC sample; gain is only

achieved when, due to lane multiplexing, the system

becomes I/O limited. In that situation, being able to send out

12−bit pixels using only 10 bits, can be useful to boost the

frame rate. When companding mode is enabled, the

precision of the digital output is 1 Least Significant Bit

(LSB) in the low light area, but towards the upper region, the

granularity gradually increases to 2, 4, and 8 LSBs as shown

in Figure 26. In all cases the ADC quantization steps will be

less than the photon shot noise performance of the pixel.

Figure 26. ADC Granularity − Companding Mode

4095

2048

1024

512

256

Signal (ADU)

10−BIT MODE

The sensor can operate in true 10−bit mode. Unlike

companding mode in 10−bit mode the ADC works in 10−bit.

This, combined with a reduced line time, allows an increase

in frame rate at the expense of 50% higher temporal noise.

The framerate for the full resolution (12 Megapixels) is 100

FPS when operating in 24 lanes and 30 FPS when operating

in 6 lanes.

Extra information about how to implement 10−bit can be

found in the XGS 12000, XGS 9400 and XGS 8000 INI file.

FRAME RATE

Assuming the readout of a frame takes longer than the

integration, the frame rate can be influenced by changing

one or more of the following parameters:

• Vertical resolution (number of lines in ROI)

• Number of data output lanes (24 / 18 / 12 / 6) or mux

mode (4:4 / 4:3 / 4:2 / 4:1)

The frame rate scales linearly with the number of lines

(vertical direction) but not with the number of columns

(horizontal direction) due to the column ADC architecture.

Using the sensor with a reduced number of data lanes will

lower the frame rate.

Alternatively, the frame time can be configured through

line_time and frame_time. The line time should be large

enough in order to process a full line and the frame time

should be configured such that at least all ROIs can be read

out and that the maximum integration can be scheduled in.

When one of the two conditions are violated the sensor gives

either priority to the readout or the integration (int_priority).

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