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L9374LF Datasheet(PDF) 55 Page - STMicroelectronics |
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L9374LF Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 80 page  DocID025414 Rev 1 55/80 L9374LF Circuit description 79 Figure 36. Test failed: high resistive load / undercurrent A failed test sequence for under current condition The test sequence: 1. Disable Edge Shaping (Command address 2, bits D8 & D7 = ‘10’) 2. Initiate SVDT (Command address 2; bits D1 & D0 = ‘10’) 3. Qx switches on at the next sync-signal (sequence of actuation: Q1..Q4) 4. The output current increases but does not reach the undercurrent value, IUC. 5. After ty the output is switched off. 6. After the output is disabled if the output clamps the voltage to VZ (35V) a Dx_Loss is detected. 7. If an Over temperature is not detected then the SDVT test is passed 8. The SVDT will then test at Qx+1 until all 4 outputs have been tested. Criterion: the current value does not reach the undercurrent value within time ty SPI: Status registers 1 - 4, UC_Qx bit is set. |
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