L9374LF datasheet(31/80 Pages) STMICROELECTRONICS

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L9374LF

Circuit description

Figure 16. Sync-failure + re-synchronization

Re-synchronizing

The master sets the SYNC_TRIG bit to ‘1’ (section 5.1.1) to re-initialize the sync counter.

This re-synchronizes the L9374LF synchronization controller to the master. When this bit is

set three counters are reset: the PWM counter (output frequency and duty cycle),

synchronization counter and the duration counter. The SYNC_TRIG bit is reset (set to ‘0’) by

the L9374LF upon re-synchronization.

The picture below shows the behavior of the output when the synchronization is done. The

time tx is anything lower than 250 μs.

Figure 17. Behavior of the output when the synchronization is done

4.3.2

Time shift between output actuation

The actuations of the outputs are time shifted by 90° (typ. 62.5 μs) to offset their effect on

the supply during switching. This balances the incremental switching current and reduces

the EME generated by the switching of these channels. The new duty cycle or target current

also becomes valid with this 90 degree time shift after the SYNC_SIG.

L9374LF Datasheet(PDF) 31 Page - STMicroelectronics