L9960 datasheet(82/95 Pages) STMICROELECTRONICS

82 / 95 page

Functional description

L9960, L9960T

82/95

DS11115 Rev 10

Table 97. SPI electrical characteristics

Symbol

Parameters

Conditions

Min.

Max.

Value

fSCLK

Clock frequency (50% duty cycle)

SPI has to work for all

frequencies

MHz

tsdo_trans

SDO rise and fall time

20% to 80% VSDOH

guaranteed by design,

20pF…150pF load

535

tclh

Minimum time SCLK = HIGH

tcll

Minimum time SCLK = LOW

tpcld

Propagation delay – incl. rise/fall time

(SCLK to data at SDO active)

150pF load

tcsdv

NCS = LOW to output SDO active (SDO

gets the same value as the last value

from the previous communication)

150pF load

tsclch

SCLK low before NCS low

(setup time SCLK to NCS change H/L)

-75

thclcl_app

SCLK change L/H after NCS = low

VHDL relevant(1)

950

tscld

SDI input setup time

(SCLK change H/L after SDI data valid)

-15

thcld

SDI input hold time

(SDI data hold after SCLK change H/L)

-15

tsclcl

SCLK low before NCS high

100

thclch

SCLK high after NCS high

100

tpchdz

NCS L/H to SDO @ high impedance

tonNCS

NCS min. high time

VHDL relevant (1)

950

Capacitance at SDI; SDO; SCLK; NCS

tfNCS

NCS Filter time (Pulses

 tfNCS are

ignored)

-10

tSPI_switch

Minimum Input Rise and Fall time;

20-80% at SDI; SCLK; NCS

tSPI_ovuv

Minimum input over/undershoot

guaranteed by design

-200

200

Tcc

Communication check timer

1. Application relevant: VHDL design needs at least 4 clock cycles (e.g. System Clock 5MHz) to process assertion of NCS

(low active Chip Select).

L9960 Datasheet(PDF) 82 Page - STMicroelectronics

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