SPSB081 datasheet(50/135 Pages) STMICROELECTRONICS

50 / 135 page

<WD type 2>: 91H (open window. 10 ms, closed window: 5 ms)

<WD type 1> indicates the long open window (timeout) which is opened at the start of the watchdog. The binary

value of WT[5:0] times 5 ms indicates the typical value of the timeout time.

<WD type 2> describes the default timing of the window watchdog.

The binary value of CW[2:0] times 5 ms defines the typical closed window time (tCW) and OW[2:0] times 5 ms

defines the typical open window time (tOW). See figure below where tCW = TEFW and tOW = TLFW - TEFW

Figure 30. Window watchdog operation

The watchdog trigger bit location is defined by the <WD bit pos. X> registers.

Table 25. WD bit position

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WB1

WB0

WBA5

WBA4

WBA3

WBA2

WBA1

WBA0

Defines the register addresses of the WD trigger bits

WBA5

WBA4

WBA3

WBA2

WBA1

WBA0

Defines the stop address of the address range (previous<WD bit pos. X> is

a WB = ‘01’). The consecutive <WD bitpos. X> has to be a WB = ‘11’

WBP 4

WBP3

WBP2

WBP1

WBP0

Defines the binary bit position of the WD trigger bit within the

<WD bit pos 1>: 41H; watchdog trigger bit located at address 01H (CR1)

<WD bit pos 2>: C0H; watchdog trigger bit location is bit0.

<WD bit pos 3>: 7FH; watchdog trigger bit located at address 3FH (Config register)

<WD bit pos 4>: C0H; watchdog trigger bit location is bit0.

SPSB081

Address definition

DS14048 - Rev 1

page 50/135

SPSB081 Datasheet(PDF) 50 Page - STMicroelectronics

SPSB081 Datasheet(HTML) 50 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL