STM32W108HB datasheet(136/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

9.11

Serial controller: Universal asynchronous receiver/

transmitter (UART) registers

9.11.1

Serial controller UART status register (SC1_UARTSR)

Address offset: 0xC848

Reset value:

0x0000 0040

Reserved

IDLE

OVR

TXE

RXNE

CTS

Bits [31:7] Reserved, must be kept at reset value

Bit 6 IDLE: Idle line detected flag

This bit is set by hardware when both the transmit FIFO and the transmit serializer are empty.

An interrupt is generated if IDLEIE=1 in the SCx_IER register.

0: No UART idle line is detected

1: UART idle line is detected

Bit 5 PE: Parity error flag

This bit is set when the byte in the data register is received with a parity error. This bit is

updated when the data register is read, and is cleared if the receive FIFO is empty. An

interrupt is generated if PEIE=1 in the SCx_IER register.

0: No UART parity error

1: UART parity error

Bit 4 FE: Frame error flag

This bit is set when the byte in the data register is received with a frame error. This bit is

updated when the data register is read, and is cleared if the receive FIFO is empty. An

interrupt is generated if FEIE=1 in the SCx_IER register.

0: No UART frame error

1: UART frame error

Bit 3 OVR: Overrun error flag

This bit is set when the receive FIFO has been overrun. This occurs if a byte is received when

the receive FIFO is full. This bit is cleared by reading the data register. An interrupt is

generated if OVRIE=1 in the SCx_IER register.

0: No overrun error occurred

1: Overrun error occurred

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