STM32W108HB datasheet(137/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Serial interfaces

Doc ID 16252 Rev 14

137/278

9.11.2

Serial controller UART control register (SC1_UARTCR)

Address offset: 0xC85C

Reset value:

0x0000 0000

Bit 2 TXE: Transmit data register empty flag (transmitters)

This bit is set when the transmit FIFO has space for at least one byte. An interrupt is

generated if TXEIE=1 in the SCx_IER register.

0: UART FIFO registers not empty

1: UART FIFO registers empty

Bit 1 RXNE: Receive data register not empty flag (receivers)

This bit is set when the receive FIFO contains at least one byte. An interrupt is generated if

RXNEIE=1 in the SCx_IER register.

0: Data is not received

1: Received data is ready to be read

Bit 0 CTS: Clear to send flag

This bit is set by hardware when the nCTS input toggles.

0: No change occurred on the nCTS status line

1: A change occurred on the nCTS status line

Reserved

AHFCE

HFCE

PCE

STOP

nRTS

Bits [31:7] Reserved, must be kept at reset value

Bit 6 AHFCE: Automatic hardware flow control enable

It is set and cleared by software.

0: Automatic hardware flow control disabled

1: Automatic hardware flow control enabled

Bit 5 HFCE: Hardware flow control enable

It is set and cleared by software.

0: Hardware flow control disabled

1: Hardware flow control enabled

Bit 4 PS: Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE

bit set). It is set and cleared by software.

0: Even parity

1: Odd parity

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