STM32W108HB datasheet(170/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

10.1.5

Input capture mode

In input capture mode, a capture/compare register (TIMx_CCRy) latches the value of the

counter after a transition is detected by the corresponding ICy signal. When a capture

occurs, the corresponding CCyIF flag in the TIMx_SR register is set, and an interrupt

request is sent if enabled.

If a capture occurs when the CCyIF flag is already high, then the missed capture flag CCyIM

in the TIMx_MISSR register is set. CCyIF can be cleared by software writing a 1 to its bit or

reading the captured data stored in the TIMx_CCRy register. To clear the CCyIF bit, write a

1 to it.

The following example shows how to capture the counter value in the TIMx_CCR1 when the

TI1 input rises.

●

Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S

bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,

the channel is configured in input and the TIMx_CCR1 register becomes read-only.

●

Program the required input filter duration with respect to the signal connected to the

timer, when the input is one of the TIy (ICyF bits in the TIMx_CCMR1 register).

Consider a situation in which, when toggling, the input signal is unstable during at most

5 internal clock cycles. The filter duration must be longer than these 5 clock cycles. The

transition on TI1 can be validated when 8 consecutive samples with the new level have

been detected (sampled at PCLK frequency). To do this, write the IC1F bits to 0011 in

the TIMx_CCMR1 register.

●

Select the edge of the active transition on the TI1 channel by writing the CC1P bit to 0

in the TIMx_CCER register (rising edge in this case).

●

Program the input prescaler: In this example, the capture is to be performed at each

valid transition, so the prescaler is disabled (write the IC1PSC bits to 00 in the

TIMx_CCMR1 register).

●

Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

●

If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_IER

●

When an input capture occurs:

–

The TIMx_CCR1 register gets the value of the counter on the active transition.

–CC1IF flag is set (capture/compare interrupt flag). The missed capture/compare

flag CC1IM in TIMx_MISSR is also set if another capture occurs before the CC1IF

flag is cleared.

–

An interrupt may be generated if enabled by the CC1IF bit.

To detect missed captures reliably, read captured data in TIMx_CCRy before checking the

missed capture/compare flag. This sequence avoids missing a capture that could happen

after reading the flag and before reading the data.

Note:

Software can generate IC interrupt requests by setting the corresponding CCyG bit in the

TIMx_EGR register.

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