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STM32W108HB Datasheet(PDF) 174 Page - STMicroelectronics

Part # STM32W108HB
Description  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108HB Datasheet(HTML) 174 Page - STMicroelectronics

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General-purpose timers
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
174/278
Doc ID 16252 Rev 14
This allows software to force a PWM output to a particular state while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode: up-counting configuration
Up-counting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Up-counting
mode on page 159.
The following example uses PWM mode 1. The reference PWM signal OCyREF is high as
long as TIMx_CNT < TIMx_CCRy, otherwise it becomes low. If the compare value in
TIMx_CCRy is greater than the auto-reload value in TIMx_ARR, then OCyREF is held at 1.
If the compare value is 0, then OCyREF is held at 0. Figure 36 shows some edge-aligned
PWM waveforms in an example, where TIMx_ARR = 8.
Figure 36.
Edge-aligned PWM waveforms (ARR = 8)
PWM edge-aligned mode: down-counting configuration
Down-counting is active when the DIR bit in the TIMx_CR1 register is high. Refer to Down-
counting mode on page 161 for more information.
In PWM mode 1, the reference signal OCyREF is low as long as TIMx_CNT > TIMx_CCRy,
otherwise it becomes high. If the compare value in TIMx_CCRy is greater than the auto-
reload value in TIMx_ARR, then OCyREF is held at 1. Zero-percent PWM is not possible in
this mode.
PWM center-aligned mode
Center-aligned mode is active except when the CMS bits in the TIMx_CR1 register are 00
(all configurations where CMS is non-zero have the same effect on the OCyREF/OCy
signals). The compare flag is set when the counter counts up, when it counts down, or when
it counts up and down, depending on the CMS bits configuration. The direction bit (DIR) in
the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer
to Center-aligned mode (up/down counting) on page 162 for more information.
Counter register
‘1
0
12
34
5
6
7
8
0
1
‘0
OCxREF
CCyIE
OCxREF
CCyIE
OCxREF
OCxREF
TIMx_CCRy=4
TIMx_CCRy=8
CCyIE
CCyIE
TIMx_CCRy>8
TIMx_CCRy=0



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